Agent/ Attorney Address Line 1:465 California Street
Agent/ Attorney Address Line 2:Suite 700
Agent/ Attorney City:San Francisco
Agent/ Attorney State/ Province:CALIFORNIA
Agent/ Attorney Country:UNITED STATES OF AMERICA
Agent/ Attorney Postal Code:94104
Agent/ Attorney Email:cadence@cipllp.com
Position Info
Prevailing Wage Track Number:P10021068130229
Prevailing Wage SOC Code :17-2072
Prevailing Wage SOC Title :Electronics Engineers, Except Computer
Prevailing Wage Skill Level:Level IV
Prevailing Wage:172245
Prevailing Wage Unit of Pay:Year
Prevailing Wage Source:OES
Prevailing Wage Other Source:
Prevailing Wage Determination Date :2021-08-04
Prevailing Wage Expiration Date :2022-06-30
Wage Offer From:173731
Wage Offer To:193731
Wage Offer Unit of Pay:Year
Workstie Address Line 1:2655 Seely Avenue
Worksite Address Line 2:
Worksite City :San Jose
Worksite State:CALIFORNIA
Worksite Postal Code:95134
Job Title:Sr. Principal Solutions Engineer
Minimum Education:Bachelor's
Other Degree/ Diploma:
Major Field of Study:Please see H.14
Required Training:N
Required Training Month:
Required Field of Training:
Required Experience :Y
Required Expreience Months :84
Accept Alternate Field of Study:Y
Accept Alternate Major:Please see H.14
Alternate Combination of Education/ Experience:N
Required Alternate Level of Education :
Other Alternate Level of Education:
Acceptable Years of Experience:
Accept Foreign Educationa:Y
Acceptable Alternate Occupation:Y
Acceptable Alternate Occupation Month:84
Accept Alternate Job Title:Please see H.14
Normal Requirements of Job Opportunity:N
Required Foreign Language:N
Specific Skills:MINIMUM REQUIREMENTS Bachelors degree in Electronic Engineering, Electrical Engineering, or related field, plus seven 7 years of progressive, postbaccalaureate experience in the job offered, or in a related solution engineering occupation.br br SPECIAL REQUIREMENTSbr br Following skills must have been gained through five 5 years of experiencebr br 1. Synthesis using Verilog and VHDL hardware description languages HDL. Logical and physical synthesis using Cadence Genus tool and Digital Implementation using Cadence Innovus toolsbr 2. Static Timing Analysis concepts and timing closure using Cadence SignOff tools, Tempus, and RC extraction using Quantus toolsbr 3. SoC tapeout experience, including all physical design implementation activities from RTL registertransferlevel to GDS Graphic Database Systembr br Following skills must have been gained through three 3 years of experiencebr br 4. Coding to automate the design flow and methodologies using C, Tcl or Perl languagesbr 5. Leading technical campaigns that involve working closely with RD and customer to develop new technologiesbr 6. Semiconductor and VLSI design understanding. Knowledge of semiconductors processes and transistor working for advanced technology nodesbr 7. Understanding of various processes involved in Chip design cyclebr br Must be available to work on projects at various, unanticipated sites throughout the United States.
Combination Occupation :N
Offered to Applied Foreign Worker:Y
ForeignWorker Live on Premises :N
Live in Domestic Service Worker:N
Employment Contract :
Professional Occupation :Y
College/ University Teacher:N
Competitive Process:
Basic Recruitment Process :
Teacher Select Date:
Teacher Publish Journal Name:
Additional Recruitment Information:
Job Oder Start Date:2021-08-09
Job Oder End Date:2021-09-10
Sunday Edition Newspaper:Y
First Newspaper Name:The Mercury News
First Advertisement Start Date:2021-08-22
Second Newspaper Name:The Mercury News
Second Advertisement Type:Newspaper
Second Ad Start Date:2021-08-29
Job Fair From Date:
Job Fair to Date:
On Campus Recruiting from Date:
On Campus Recruiting to Date:
Employer Website from Date:
Employer Website to Date:
Pro. Org. Ad from Date:2021-08-21
Pro.Org. Ad to Date:2021-08-31
Job Search Website from Date:2021-08-21
Job Search Website to Date:2021-08-31
Private Employment Firm from Date:
Pricate Employment Firm to Date:
Employee Referral Program from Date:
Employee Referral Program to Date:
Campus Placement from Date:
Campus Placement to Date:
Local Ethnic Newspaper from Date:2021-08-27
Local Ethnic Newspaper to Date:2021-08-27
Radio/TV Ad from Date:
Radio/TV Ad to Date:
Employer Received the Payment:N
Payment Details:
Bargaining Representative Notified:N/A
Posted Notice at Worksite:Y
Layoff in Past Six Months:N
US Worker Considered:
Country of Citizenship:INDIA
Foreign Worker Birth Country:INDIA
Class of Admission :O-1
Employee Info
Foreign Worker Education:Bachelor's
Foreign Worker Education Other:
Foreign Worker Major:ELECTRONIC ENGINEERING
Year of Compelted Education:2008
Foreign Worker Istitution of Eduation:THAPAR UNIVERSITY, PATIALA
Foreign Worker Education Instution Address Line 1:POST BOX NO 32
