Prevailing Wage SOC Title :Electronics Engineers, Except Computer
Prevailing Wage Skill Level:N/A
Prevailing Wage:165022
Prevailing Wage Unit of Pay:Year
Prevailing Wage Source:Other
Prevailing Wage Other Source:Radford Global Technology Survey - 12/1/2020
Prevailing Wage Determination Date :2021-08-24
Prevailing Wage Expiration Date :2022-06-30
Wage Offer From:165022
Wage Offer To:205022
Wage Offer Unit of Pay:Year
Workstie Address Line 1:690 East Middlefield Road
Worksite Address Line 2:
Worksite City :Mountain View
Worksite State:CALIFORNIA
Worksite Postal Code:94043
Job Title:ASIC Physical Design Engineer, Staff
Minimum Education:Master's
Other Degree/ Diploma:
Major Field of Study:Computer Engg, Electrical/Electronic Engg, or related
Required Training:N
Required Training Month:
Required Field of Training:
Required Experience :Y
Required Expreience Months :48
Accept Alternate Field of Study:Y
Accept Alternate Major:Computer Engg, ElectricalElectronic Engg, or related
Alternate Combination of Education/ Experience:Y
Required Alternate Level of Education :Bachelor's
Other Alternate Level of Education:
Acceptable Years of Experience:6
Accept Foreign Educationa:Y
Acceptable Alternate Occupation:Y
Acceptable Alternate Occupation Month:48
Accept Alternate Job Title:Any joboccupation re ASIC physical design
Normal Requirements of Job Opportunity:N
Required Foreign Language:N
Specific Skills:EDUCATION Masters or foreign equivalent degree in Computer Engineering, ElectricalElectronic Engineering or a related field.br br EXPERIENCE Four years of experience in ASIC physical design.br br ALTERNATE EDUCATION AND EXPERIENCE Bachelors or foreign equivalent degree in Computer Engineering, ElectricalElectronic Engineering or a related field and six years of progressive, postbaccalaureate experience in ASIC physical design.br br SPECIFIC SKILLS This position also requires education or experience in 1 physical implementation flow and methodology development at advanced technology nodes 10nm and below; 2 physical verification at advanced technology nodes 10nm and below; 3 timing closure and signoff; 4 VLSI concepts, including IR drop, blocklevel and chiplevel implementation, clock tree spec development; 5 the full design cycle from RTL to GDSII; 6 development of timing constraints; 7 low power designs; and 8 high speed clock design and distribution.br br Any suitable combination of education, experience, or training is acceptable.
Combination Occupation :N
Offered to Applied Foreign Worker:Y
ForeignWorker Live on Premises :N
Live in Domestic Service Worker:N
Employment Contract :
Professional Occupation :Y
College/ University Teacher:N
Competitive Process:
Basic Recruitment Process :
Teacher Select Date:
Teacher Publish Journal Name:
Additional Recruitment Information:
Job Oder Start Date:2021-08-25
Job Oder End Date:2021-09-29
Sunday Edition Newspaper:Y
First Newspaper Name:Mercury News San Jose
First Advertisement Start Date:2021-09-26
Second Newspaper Name:Mercury News San Jose
Second Advertisement Type:Newspaper
Second Ad Start Date:2021-10-03
Job Fair From Date:
Job Fair to Date:
On Campus Recruiting from Date:
On Campus Recruiting to Date:
Employer Website from Date:
Employer Website to Date:
Pro. Org. Ad from Date:
Pro.Org. Ad to Date:
Job Search Website from Date:
Job Search Website to Date:
Private Employment Firm from Date:
Pricate Employment Firm to Date:
Employee Referral Program from Date:2021-09-22
Employee Referral Program to Date:2021-10-04
Campus Placement from Date:
Campus Placement to Date:
Local Ethnic Newspaper from Date:2021-09-29
Local Ethnic Newspaper to Date:2021-10-05
Radio/TV Ad from Date:2021-09-30
Radio/TV Ad to Date:2021-09-30
Employer Received the Payment:N
Payment Details:
Bargaining Representative Notified:N/A
Posted Notice at Worksite:Y
Layoff in Past Six Months:N
US Worker Considered:
Country of Citizenship:INDIA
Foreign Worker Birth Country:INDIA
Class of Admission :H-1B
Employee Info
Foreign Worker Education:Master's
Foreign Worker Education Other:
Foreign Worker Major:ELECTRICAL AND ELECTRONIC ENGINEERING
Year of Compelted Education:2011
Foreign Worker Istitution of Eduation:NATIONAL INSTITUTE OF TECHNOLOGY, DURGAPUR
Foreign Worker Education Instution Address Line 1:MAHATMA GANDHI AVENUE
Foreign Worker Education Institution Address Line 2:
