Prevailing Wage SOC Title :Electronics Engineers, Except Computer
Prevailing Wage Skill Level:Level IV
Prevailing Wage:166026
Prevailing Wage Unit of Pay:Year
Prevailing Wage Source:OES
Prevailing Wage Other Source:
Prevailing Wage Determination Date :2020-09-18
Prevailing Wage Expiration Date :2021-06-30
Wage Offer From:166026
Wage Offer To:246500
Wage Offer Unit of Pay:Year
Workstie Address Line 1:2485 Augustine Drive
Worksite Address Line 2:
Worksite City :Santa Clara
Worksite State:CALIFORNIA
Worksite Postal Code:95054
Job Title:SMTS Silicon Design Engineer
Minimum Education:Master's
Other Degree/ Diploma:
Major Field of Study:Computer Engineering, see H.14
Required Training:N
Required Training Month:
Required Field of Training:
Required Experience :Y
Required Expreience Months :60
Accept Alternate Field of Study:Y
Accept Alternate Major:Computer Science, see H.14
Alternate Combination of Education/ Experience:Y
Required Alternate Level of Education :Bachelor's
Other Alternate Level of Education:
Acceptable Years of Experience:7
Accept Foreign Educationa:Y
Acceptable Alternate Occupation:Y
Acceptable Alternate Occupation Month:60
Accept Alternate Job Title:See H.14
Normal Requirements of Job Opportunity:N
Required Foreign Language:N
Specific Skills:MASTERS DEGREE OR FOREIGN EQUIVALENT IN COMPUTER ENGINEERING, COMPUTER SCIENCE, ELECTRONICS ENGINEERING, OR ELECTRICAL ENGINEERING AND FIVE 5 YEARS OF EXPERIENCE INVOLVING THE FOLLOWING UVM, SYSTEM VERILOG, VHDL, OR VERILOG; PYTHON, C, C, PERL, TCL, OR SHELL; COORDINATION OF TECHNICAL PROJECTS ASSOCIATED WITH PRODUCT DEVELOPMENT LIFECYCLES, INCLUDING DETERMINING TECHNICAL PRIORITIES; RTL VERIFICATION, FUNCTIONAL VERIFICATION OF MICROPROCESSORS, HARDWARE VERIFICATION, GRAPHICS IP ARCHITECTURE VERIFICATION, MEMORY VERIFICATION IP, OR DESIGN FLOWSMETHODOLOGIES FOR CHIP VERIFICATION; AND EDA TOOLS AND CAD TECHNOLOGY.br br EMPLOYER WILL ACCEPT ALTERNATE COMBINATION OF EDUCATION OR EXPERIENCE BACHELORS DEGREE OR FOREIGN EQUIVALENT IN COMPUTER ENGINEERING, COMPUTER SCIENCE, ELECTRONICS ENGINEERING, OR ELECTRICAL ENGINEERING AND SEVEN 7 YEARS OF PROGRESSIVE POSTBACCALAUREATE EXPERIENCE INVOLVING THE FOLLOWING UVM, SYSTEM VERILOG, VHDL, OR VERILOG; PYTHON, C, C, PERL, TCL, OR SHELL; COORDINATION OF TECHNICAL PROJECTS ASSOCIATED WITH PRODUCT DEVELOPMENT LIFECYCLES, INCLUDING DETERMINING TECHNICAL PRIORITIES; RTL VERIFICATION, FUNCTIONAL VERIFICATION OF MICROPROCESSORS, HARDWARE VERIFICATION, GRAPHICS IP ARCHITECTURE VERIFICATION, MEMORY VERIFICATION IP, OR DESIGN FLOWSMETHODOLOGIES FOR CHIP VERIFICATION; AND EDA TOOLS AND CAD TECHNOLOGY.br br EMPLOYER WILL ACCEPT ANY SUITABLE COMBINATION OF EDUCATION, TRAINING, OR EXPERIENCE.br br H.10B ACCEPTED OCCUPATIONS JOB OFFERED OR ALTERNATE OCCUPATION OF AT ANY LEVEL DESIGN ENGINEER, VERIFICATION ENGINEER, DFT ENGINEER, APPLICATION ENGINEER, ASIC ENGINEER, SYSTEMS ENGINEER, PRODUCT ENGINEER, PHYSICAL DESIGN ENGINEER, TEST ENGINEER, IC ENGINEER, PRINCIPAL ENGINEER, INTERN, TECHNICAL LEAD, COOP ENGINEER, RESEARCH ASSISTANT, RD ENGINEER, MEMBER OF TECHNICAL STAFF, OR ENGINEER.
Combination Occupation :N
Offered to Applied Foreign Worker:Y
ForeignWorker Live on Premises :N
Live in Domestic Service Worker:N
Employment Contract :
Professional Occupation :Y
College/ University Teacher:N
Competitive Process:
Basic Recruitment Process :
Teacher Select Date:
Teacher Publish Journal Name:
Additional Recruitment Information:
Job Oder Start Date:2021-01-11
Job Oder End Date:2021-02-15
Sunday Edition Newspaper:Y
First Newspaper Name:San Jose Mercury News
First Advertisement Start Date:2020-12-06
Second Newspaper Name:San Jose Mercury News
Second Advertisement Type:Newspaper
Second Ad Start Date:2020-12-13
Job Fair From Date:
Job Fair to Date:
On Campus Recruiting from Date:
On Campus Recruiting to Date:
Employer Website from Date:
Employer Website to Date:
Pro. Org. Ad from Date:
Pro.Org. Ad to Date:
Job Search Website from Date:2020-12-06
Job Search Website to Date:2021-01-05
Private Employment Firm from Date:
Pricate Employment Firm to Date:
Employee Referral Program from Date:
Employee Referral Program to Date:
Campus Placement from Date:
Campus Placement to Date:
Local Ethnic Newspaper from Date:2020-12-11
Local Ethnic Newspaper to Date:2020-12-11
Radio/TV Ad from Date:2020-12-21
Radio/TV Ad to Date:2020-12-21
Employer Received the Payment:N
Payment Details:
Bargaining Representative Notified:N/A
Posted Notice at Worksite:Y
Layoff in Past Six Months:N
US Worker Considered:
Country of Citizenship:INDIA
Foreign Worker Birth Country:INDIA
Class of Admission :H-1B
Employee Info
Foreign Worker Education:Bachelor's
Foreign Worker Education Other:
Foreign Worker Major:ELECTRONIC ENGINEERING
Year of Compelted Education:1999
Foreign Worker Istitution of Eduation:BHAVNAGAR UNIVERSITY
Foreign Worker Education Instution Address Line 1:SHANTILAL SHAH ENGINEERING COLLEGE, NEW SIDSAR CAMPUS
Foreign Worker Education Institution Address Line 2:POST VARTEJ, SIDSAR, BHAVNAGAR, GUJARAT, IN
